Ferroelectric memory devices are nonvolatile devices that retain data after supply of power is stopped. They may also be operated at a supply voltage for the device, like some DRAM or SRAM devices. Ferroelectric memory devices may be used in, for example, smart cards or other memory cards.
FIGS. 1 through 4 are cross-sectional views illustrating a method of fabricating a conventional ferroelectric memory device.
Referring to FIG. 1, a device isolation layer 13 is formed at predetermined regions of a semiconductor substrate 11 to define active regions. Insulated gate electrodes 15, which serve as word lines, are formed to cross over the active regions and the device isolation layer 13. Impurity ions are implanted into the active region between the gate electrodes 15, to form source/drain regions 17s and 17d. A first lower interlayer dielectric (ILD) 19 is formed on the entire surface of the resultant structure on the source/drain regions 17s and 17d. The first lower ILD 19 is patterned to form storage node contact holes, which expose the source regions 17s. Contact plugs 21 are formed in the storage node contact holes.
Referring to FIG. 2, ferroelectric capacitors 32, which are 2-dimensionally arranged, are formed on the entire surface of the semiconductor substrate 11 including the contact plugs 21. Each of the ferroelectric capacitors 32 includes a lower electrode 27, a ferroelectric pattern 29, and an upper electrode 31, which are sequentially stacked. Each of the lower electrodes 27 covers one of the contact plugs 21. A first upper ILD 33 is formed on the entire surface of the semiconductor substrate including the ferroelectric capacitors 32. A plurality of main word lines 35, which are parallel to the gate electrodes 15, are formed on the first upper ILD 33. Each of the main word lines 35 may, for example, control four gate electrodes 15.
The upper and lower electrodes 31 and 27 may be formed of noble metals of the platinum group. Sidewalls of the ferroelectric capacitor 32 have sloped sidewalls, as illustrated in FIG. 4.
Referring to FIGS. 3 and 4, a second upper ILD 37 is formed on the entire surface of the semiconductor and the main word lines 35. The second upper ILD 37 and first upper ILD 33 are patterned to form via holes 39, which expose the upper electrodes 31. A wet etch process and a dry etch process may be performed to reduce an aspect ratio of each via hole 39. As illustrated in FIG. 3, the via hole 39 has sloped upper sidewalls 39a. A plurality of plate lines 41 are formed to cover the via holes 39. The plate lines 41 are disposed in parallel with the main word lines 35.
In another approach, the diameter of the via hole 39 may be increased to reduce an aspect ratio of the via hole 39. However, increasing the diameter may cause a short between the plate line 41 and the main word line 35. As the integration density of ferroelectric memory devices increases, it may become more difficult to properly align the via hole 39 with the upper electrode 31. Moreover, space “s” between the via hole 39 and the main word line 35 adjacent to the via hole 39 may become smaller. Increasing the diameter of the via hole 39, or misaligning the via hole 39 with the upper electrode 31, may result in the main word line 35 being exposed by the via hole 39 and a corresponding short between the plate line 41 and the main word line 35 (see FIG. 4).
Misalignment between the via hole 39 and the upper electrode 31 may also result in etching damage to the pattern 29. For example, the via hole 39 may be formed using an over-etching technique to facilitate connection between the subsequently formed plate line 41 and the upper electrode 31. During the formation of the via hole 39, the sloped sidewalls of the ferroelectric capacitor 32 may be exposed and damaged by the etching.